Strange but True
Electronic Design Automation is one of those unusual fields where to be effective you need to know many things... First you need to be an excellent programmer as the basic job is writing software. But the purpose of the software is to help designers (ASICS, Circuit Boards, Custom VSI chips, FPGAs, etc.) work more effectively so you need to be trained as a design engineer to appreciate the challenges of their job.
Well it seems circuit design involves some basic engineering rules but modeling realistic circuits today may involve 100 million transistors and processing of this information requires careful data structure design and critial performance tuning. Also many parts of the design flow to be automated are unbounded complex problems that can only be approached through knowledge of special heurstics.
Of course, today it is expected that a user-friendly GUI be presented to the user so knowledge of computer-user interface theory is needed. Finally it should be noted that EDA software is responsible for the final checking (logic validation, process design rules, etc.)before expensive chip fabrication step. So bug-free software is expected to avoid wasting millions of dollars in chip manufacturing and the Software team development process needs to be very very tight.
Each of these problems is significant in its own right but taken together creates an unusually difficult software development challenge, not for the timid..
Well, it has been my joy to deal with these challenges for more than 25 years and to have worked on virtually every speciality within the EDA tool box. My career so far has produced many design aids and following list is some of the more note-worthy examples. Some were complex systems requiring large development teams and multiple calendar years effort or individual effort invented for the "common good" as a quick effort. Most became production tools as part of some system/chip/programming design flow.
- ASSURE - Logic Equivalence Checker using combined solvers (patented technique). Differientiated by significant speed and scaleabilty over competing tools, including parallel mode for dual processor platforms
- FORSIM - HW formal verification environment using POBDDs, SAT, and simulation. The basis of several related tools with patented algorithms and grid computing feature for rapid solving on linux clusters
- UFE - Univeral Framework for developing CAD application with RTL front-end synthesis, in-memory netlist object class library, GUI and other common "building blocks"
- TIMELESS - Automatic ASIC clock tree synthesis (low skew balanced network)
- SCENERY - ESL environment for verification of UML behavior descriptions against ASIC logic design with interactive editor/navigation tool
- SYNTH - ECL logic synthesis optimized to minimize path delays (Verilog & VHDL)
- ERC - Electrical Design Rule Checker for chip logic designs
- ASAP - Chip Static Speed Analysis (high precision modeling with process variation)
- BSAP - Board Static Speed Analysis
- ULTRASIM - Fast cycle simulator for full mainframe logic designs
- HYPERSIM - Mixed level logic simulator for C code, logic gates and HW acceleration
- TGEN - Chip Test Generation (functional and delay tests) system
- ALD - Schematic editor for system logic designs (ALD format)
- TABLE - Logic entry tool to synthesize logic gates from truth tables
- FLOW - Logic entry editor for flowgraph designs conversion to logic gates
- GEDI - Interactive VLSI mask layout graphical editor
- COMPACT - Symbolic editor and compaction tool for ECL cell designs with rules-driven mask generator for "correct by construction" custom LSI
- MEDS - Micro Electronics Design System for VLSI mask layout and assembly
- ASSIST - Engineering database system, portable to several computing platforms offering efficient storage and navigation of CAD design files with hidden APIs using PREP
- PREP - Text preprocessor used to extend programming languages syntax with novel stack macro rules definintion, configurable to target syntax of specific compilers
- PLOT - Driver for Versatec Printers for multi-page PCB layouts (SCI-CARDS)
- MIDAS - Multilevel Design Automation System for logic capture and documentation
- HADES - High level system design entry and simulator
- WIRES - Rules-driven wire-wrap program generation system
- ZOTMAKER - General purpose tool for adding/updating comment blocks (zots) in source code
- HSDL - Hierarchical System Design Language simulator using proprietary RTL
- CONFIG - System for automatic configuration of mfg parts from sales orders
- TWST - Parser generator system using extended BNF with user functions